The present invention relates to a semiconductor device including a silicon nitride film containing chlorine and a method of manufacturing the same.
With progress in the degree of integration and fineness of the semiconductor device, a semiconductor device of the next era makes it absolutely necessary to develop a process technology that permits forming an interlayer insulating film (SiO2 film) having a finer contact hole of a higher aspect ratio, that permits forming a uniform silicon nitride film of a high step coverage within the contact hole made in the interlayer insulating layer, and that permits polishing the silicon nitride film by a chemical mechanical polishing (CMP) to achieve a buried shape of the silicon nitride film as designed and having a high flatness.
The particular technology is employed in the case of forming a device structure as shown in, for example, FIG. 33 showing a cross section in a direction perpendicular to the longitudinal direction of the channel of a MOS transistor included in a DRAM cell.
In the structure shown in FIG. 33, a drain diffusion layer 682 is formed in a surface region of a silicon substrate 681. Also, an interlayer insulating film (SiO2 film) 685 is formed on the surface of the silicon substrate 681. A contact hole 683 and a wiring trench 684 connected to the drain diffusion layer 682 through the contact hole 683 are formed in the interlayer insulating film 685.
A buried wiring 686 made of tungsten is formed to fill the contact hole 683 and a lower portion of the wiring trench 684. Also, a silicon nitride film 687 is formed on the side walls of the contact hole 683 and the lower portion of the wiring trench 684.
The buried wiring 686 is formed to fill completely the contact hole 683 and to fill only the lower portion of the wiring trench 684. An upper portion of the wiring trench 684, which is not filled with the buried wiring 686, is filled with a silicon nitride film 688. The silicon nitride film 688 of this kind is called a cap insulating film. The cap insulating film is intended to prevent short-circuiting between a lower capacitor electrode 689 formed on the cap insulating film and the buried wiring 686.
The cap insulating film is used as a mask in the step of forming by RIE (Reactive Ion Etching) a contact hole for the capacitor, i.e., a contact hole for connecting the lower capacitor electrode to an n+-type source diffusion layer, in the interlayer insulating film (SiO2 film) 685. Therefore, the silicon nitride film 688, which exhibits a high selectivity ratio, is used as the cap insulating film.
A Ti/TiN laminate film 690 is formed as a barrier metal film at the bottom of the contact hole 683 so as to prevent reaction between the drain diffusion layer 682 and the buried wiring 686 in the subsequent heat treating step.
Where the wiring trench 684 has an aspect ratio not smaller than 1, it was customary to form the silicon nitride film (DCS-SiN film) 688 by a low pressure chemical vapor deposition method (LPCVD method), which is a CVD method having a good step coverage and performed by using dichlorosilane (DCS) as the Si raw material.
However, the conventional method described above gives rise to problems as pointed out below.
First of all, a ratio of the polishing rate by CMP of the interlayer insulating film (SiO2) 685 to the DCS-SiN film 688 is about 30, which is not sufficiently high. Therefore, in the step of removing by CMP an excess DCS-SiN film 688 outside the wiring trench 684, the interlayer insulating film 685 fails to perform the function of a stopper. As a result, the DCS-SiN film 688 is excessively polished. In this case, the thickness of the DCS-SiN film 688 is rendered thinner than the design value, as shown in FIG. 34, giving rise to problems. For example, leakage current between the buried wiring 686 and the lower capacitor electrode 689 is increased. Also, the breakdown voltage is lowered.
What should also be noted is that, in forming the contact hole for the capacitor by etching, the DCS-SiN film 688 is used as a mask. If the DCS-SiN film 688 is excessively polished, short-circuiting is brought about in the worst case between the buried wiring 686 and the lower capacitor electrode 689, as shown in FIG. 35.
In recent years, demands for an improvement in the degree of integration and operating speed of a semiconductor device are on a sharp increase. To meet these demands, vigorous efforts are being made in an attempt to shorten the distance between adjacent device elements and to miniaturize the device element. At the same time, vigorous studies are being made in an attempt to decrease the resistance of the buried wiring and to diminish the parasitic capacitance.
In, for example, DRAM, the degree of integration is prominently increased. Therefore, in forming a contact hole, it is necessary to form a narrow stepped shape having a large aspect ratio. To meet this requirement, a silicon nitride film (SiN film) having a high selectivity ratio has come to be used in, for example, DRAM as an etching stopper film in forming a contact hole in an interlayer insulating film (e.g., TEOS oxide film) by RIE.
It is necessary for the SiN film used as an etching stopper film (RIE stopper film) of this kind to exhibit a selectivity ratio for RIE that is sufficiently high relative to an oxide film such as a BPSG film or a TEOS film. Further, in accordance with progress in the degree of integration and miniaturization of the device element, it is necessary to cover homogeneously and uniformly a narrow stepped shape having a severer aspect ratio.
To meet these requirements, it was customary in forming a contact hole to use as a RIE stopper film a relatively dense SiN film formed by the LPCVD method at about 780° C. by using dichlorosilane (DCS) and ammonia as raw materials. Where a TEOS film is etched by RIE, the RIE selectivity of the TEOS film relative to the SiN film thus formed is as high as about 7, and the SiN film was found to exhibit a permittivity of about 7.5. However, the permittivity of 7.5 is relatively large. Particularly, the capacitance between adjacent wirings or the RC delay time of the entire device element are greatly dependent in recent years on the capacitance of the RIE stopper film in accordance with miniaturization of the device element. As a matter of fact, the capacitance of the RIE stopper film appears as a delay in the operating speed of the device element in a DRAM of the 0.18 micron era et seq.
Also, use of the SiN film as a RIE stopper film leads to an increased bit line capacitance. In order to make up for the increased bit line capacitance, it is necessary to prepare a capacitor having a large capacitance, leading to disadvantages in the characteristics of the device.
Further, in the case of using a SiN film as a RIE stopper film, the conditions for RIE must be changed to those adapted for etching the SiN film after formation of an opening by etching in an oxide film such as a BPSG film or a TEOS film. It should be noted in this connection that the opening has a large aspect ratio and a small diameter, giving rise to various problems. For example, the SiN film at the bottom of the opening cannot be removed by RIE uniformly over the entire planar region, with the result that the residue of the SiN film tends to remain on the bottom portion. Also, since the silicon substrate is directly exposed to RIE, damages done to the substrate are worried about. In this case, an over-etching cannot be performed sufficiently and, thus, the SiN film partly remains unremoved, giving rise to a possibility that an unsatisfactory electrical contact will be brought about.
In the next step, a treatment with a dilute hydrofluoric acid is carried out for removing the native oxide film in the contact portion. What should be noted is that the etching rate of the DCS-SiN film formed at 780° C. by using dichlorosilane (DCS) as a raw material is 0.2 nm/min when etched with a dilute hydrofluoric acid (1/200) in contrast to about 1 nm/min for the native oxide film. Since the etching rate of the DCS-SiN film is low, the native oxide film fails to be removed in the etching step with the dilute hydrofluoric acid.
On the other hand, a high processing speed is required for a logic device, making it necessary to decrease the so-called “RC delay time”, i.e., to decrease the capacitance between adjacent wirings and the wiring resistance. For decreasing the wiring resistance, use of copper for forming the metal wiring is being studied. For using a copper wiring, a barrier layer is required for preventing oxidation of the copper wiring and for preventing diffusion of copper within the copper wiring. Use of a SiN layer is now under study as one of the barrier layers.
FIG. 36 exemplifies a structure in which a SiN film is formed as a barrier layer on a Cu wiring. The structure shown in the drawing includes a TEOS oxide film 701, a TaN film 702, a Cu wiring 703 and a SiN film 704. Even in the case of employing the Cu wiring technology, an Al wiring is partly used in the narrow pitch portion between adjacent wirings in order to decrease the RC component between adjacent wirings. Therefore, it is necessary for the SiN film 704 to be formed in the subsequent step at a temperature not exceeding the Al reflowing temperature of 450° C. Also, the interlayer insulating film that is already formed in the step of forming the wiring is formed of a low permittivity film (generally called low-k film) such as a film of FSG (Fluorine-added Silicate Glass) in order to decrease the permittivity. Since these films are formed at a low temperature, i.e., not higher than 400° C., cracks tend to be generated at temperatures not lower than 450° C. Such being the situation, the SiN film 705 must be formed at low temperatures not higher than 450° C. In general, the SiN film 705 is formed by a plasma CVD which can be easily performed at low temperatures.
In a semiconductor device, the aspect ratio of the device element separating trench and the concave portion between gate electrodes tends to be increased in accordance with miniaturization of the device element. With increase in the aspect ratio, it gradually becomes difficult to bury an insulating film such as a silicon oxide film within the trench without forming a so-called “void”.
Under the circumstances, use of an HDP (High-Density Plasma)-CVD method or a TEOS-O3 series CVD method is being tried. However, the former method gives rise to problems such as a plasma damage done to the underlying layer, a nonuniformity in the film quality and a low through-put. Also, the latter method gives rise to the problem that a heat treatment at a high temperature is required for improving the film quality after the film formation.